I/O drivers can be exposed to three modes of operation, including normal voltage mode, in which VDD is in the range of 1.6 to 2.0 V, VDDIO is 3.0 to 3.6 V, and the output from the I/O driver to the pad is at 0 to 3.6 V. The other two modes include over-voltage mode or operation in which a high voltage is fed into the pad from external circuitry while power is supplied to the driver, and back-drive mode or operation, which occurs during power up when VDD and VDDIO have not yet been applied to circuit. In particular, in over-voltage operation VDD is in the range of 1.6 to 2.0 V and VDDIO is 3.0 to 3.6 V, as in normal operation, however a voltage higher than VDDIO may be fed into the Pad (typically 3.6 to 5.5 V) by external circuitry. In back-drive operation VDD and VDDIO are both at 0V while a voltage of 0 to 5.5 V may be fed into the pad by external circuitry. This is best understood with respect to FIG. 1, which shows a simple driver circuit arrangement with multiple drivers 100, 102, 104 with their outputs connected to a bus 110 that connects to the pad.
In one prior art I/O driver described in commonly owned patent publication 7071764, the I/O driver is implemented as two PMOS transistors 200, 202 and two NMOS transistors 204, 206, as shown in simplified form in FIG. 2. The two PMOS transistors have different well voltage potentials FW3 and FW5 with respect to the pad output during normal mode. Also the gates of the PMOS and NMOS transistors are provided with different voltages, PG1, PG2, NG1, NG2. In order to avoid gate oxide breakdown or well junction breakdown during over-voltage and back-drive operation, the wells of the PMOS transistors and the gates of the PMOS and NMOS transistors are charged to different voltage levels by making use of charging circuits that are fed through a multiplexer arrangement that is depicted in simplified form by reference numerals 212 and 210.
It will be appreciated that the charging circuitry for charging the wells and gates adds an extra level of complexity and requires a substantial amount of space. The present invention seeks to provide a solution that requires a charging circuit that is less complex and less space consuming.